Printed circuit boards (hereinafter also referred to as PCBs), chip carriers, and the like (these products referred to generally herein as circuitized substrates) are typically constructed in laminate form in which several layers of dielectric material and conductive material bonded together using relatively high temperature and pressure lamination processes. The conductive layers, typically of thin copper or copper alloy, function as the circuit layers for the resulting multilayered substrate, and, if a signal layer, typically include a pattern of lines, pads, etc. (The conductive layer may also be of substantially solid construction and serve, e.g., as a power or ground layer). If a signal layer, the formed circuits may also include passive devices such as capacitors, resistors, inductors, and the like. These circuits are usually used in the formed final product for providing electrical connections to and among various devices located on the surface of the substrate, examples of such devices being integrated circuits (semiconductor chips) and modules such as chip carriers having one or more chips as part thereof. As is known, many such circuits, both internal and external, utilize what are known as film resistors as part thereof.
Film resistors, as further evidenced by the patents and pending applications listed below, are often utilized as part of substrate circuits. Film resistors are commonly used in hybrid circuits and include thick film resistors which are conventionally formed by screen-printing a resistive material on an insulating substrate and then firing the material, and thin film resistors which are conventionally formed by sputtering or vacuum-depositing a resistive material on an insulating substrate. In a different approach, it is known to provide resistors in a sheet form in which a thin, defined layer of resistive material is deposited on a thin conductor layer, typically copper, and this bi-layered member is then bonded to the substrate with the resistive material face down or directly on the substrate's upper surface. Subsequent processing is used to define from this large bi-layered member a defined series of individual resistors each including a pair of spaced apart, opposed conductors (“lands”) on the resulting resistive material configuration, with electrical current then designed to run from one conductor to another, through the resistive material of course. The conductors in turn are electrically coupled to remaining circuitry, e.g., signal lines, which form the desired circuit pattern on the substrate's surface.
In many circuits, it is often necessary to adjust the resistance of the film resistors in the circuit. To increase the resistance of a film resistor, the resistor is “trimmed”, often by forming a slot across the electrical current path in the resistor to make the effective width of the resistor (and the current path there-through) smaller and thereby increasing resistance (see more below). This channel may be formed by mechanical abrasion, chemical etching, or laser vaporization (ablation) of the resistor material, as discussed in greater detail below. At present, film resistors typically require resistive material of different ranges and values. The final resistance value depends on the aspect ratio of the resistor and the sheet resistivity of the resistive material. When a wide range of values is required in the manufacture of a hybrid circuit, the deposition of resistor material must be repeated for each different range of resistance values. Such resistors are processed to lower values than the circuit calls for and after completion of the manufacturing process are “trimmed up” in value to the resistance required in the circuit. This method has been found to be costly and time consuming in manufacturing hybrid film circuits because of the need for two or more different resistor compositions. Such resistors are thus relatively expensive to produce and to position on the surface of a substrate layer (e.g., dielectric) to be connected to the selected parts of the circuit. That is, precisely forming such resistors on selected locations of high density circuits with exacting resistor values is considered difficult when forming such high density circuit patterns as are so often required in many of today's micro-miniature circuit products.
As mentioned in the preceding paragraph, the use of lasers for “trimming” resistors is known. Generally speaking, laser trimming is used in two ways to produce a change (higher ohms) in thick (polymer) resistors: (a) by reducing or changing the path of current through the resistor in terms of magnitude and direction; and (b) by reducing or changing the cross-sectional area perpendicular to the direction of current flow. The first method, mentioned above, is typically performed by making a trim slice through a portion of the resistor to create a localized reduction in the cross-sectional area relative to the direction of current flow. This method, however, may distort the electrical field around the slice cut and produce undesirable variations in the impedance of the resistor at higher signal frequencies. The second approach performs a planar cut to reduce the cross-sectional area of the resistor in the direction of current flow. Because only the magnitude of the current is affected and not the direction, high frequency impedance will not typically be affected in a significant manner.
The present invention defines the formation of highly precise, film resistor values for individual film resistors which form part of a circuit pattern on a layer for use in a circuitized substrate. As defined, the resulting resistors may form part of internal circuits (e.g., when the layer is bonded to other dielectric and conductive layers to form a larger, thicker final product) and are also applicable to the formation of such resistors on the exterior circuits of such products. The invention is applicable to both thick and thin film resistors.
With particular respect to internal resistors, formation thereof is especially desired for many of today's substrate designs. Known discrete passive devices, such as capacitors, resistors, inductors, and the like, typically occupy a relatively high percentage of the exterior surface area of the completed multilayered substrate product, which is undesirable from a future design aspect because of the aforementioned need for increased miniaturization. In order to increase the available exterior substrate surface area (also often referred to as “real estate”), there have been a variety of efforts to use internal circuits with such devices as part thereof. A capacitor or resistor designed for disposition within (e.g., between selected layers) a substrate may thus be referred to as an embedded integral passive component, or, more simply, an embedded resistor or capacitor. Such a capacitor thus provides internal capacitance while a resistor provides internal resistance. The result of this internal positioning is that it is unnecessary to also position such devices externally on the PCB's outer surface(s), thus saving valuable PCB surface area. Examples of these are also shown in the patents listed below. As understood from the teachings herein, the layered structures including circuits having the resistors formed in accordance with the instant teachings may be incorporated within larger substrate structures, e.g., as part of a lamination process with other layers.
With respect to resistor materials for thick and/or thin resistors of the type defined herein, commercially available dielectric powders are known, in addition to a wide range of other commercially available products (mentioned below). These are known to be produced by a high-temperature, solid-state reaction of a mixture of the appropriate stoichiometric amounts of oxides or oxide precursors (e.g., carbonates, hydroxides or nitrates) of barium, calcium, titanium, and the like. In such calcination processes, the reactants are wet-milled to accomplish a desired final mixture. The resulting slurry is dried and fired at elevated temperatures, sometimes as high as 1,300 degrees Celsius (C), to attain the desired solid state reactions. Thereafter, the fired product is milled to produce a powder. Although the pre-fired and ground dielectric formulations produced by solid phase reactions are acceptable for many electrical applications, these suffer from several disadvantages. First, the milling step may serve as a source of contaminants, which can adversely affect electrical properties. Second, the milled product may consist of irregularly shaped fractured aggregates which are often too large in size and possess a wide particle size distribution, 500-20,000 nm. Consequently, films produced using these powders are limited to thicknesses greater than the size of the largest particle. Thirdly, powder suspensions or composites produced using pre-fired ground ceramic powders must be used immediately after dispersion, due to the high sedimentation rates associated with large particles. The stable crystalline phase of barium titanate for particles greater than 200 nm is tetragonal and, at elevated temperatures, a large increase in dielectric constant occurs due to a phase transition. It is thus clear that methods of making PCBs which rely on the advantageous features of using nano-powders as part of the circuitized substrate's internal components or the like may possess various undesirable aspects which are detrimental to providing a circuitized substrate with optimal functioning capabilities when it comes to internal resistance, capacitance or other electrical properties.
The above is particularly true when the desired final product includes thru-holes as part thereof, these thru-holes passing through selected layers in the product and interconnecting selected conductors such as lines or pads from one layer to another, sometimes interconnecting several layers. The thru-holes consume further space, especially when used in high density patterns such as up to 5,000 thru-holes per square inch of substrate surface area. As is known, extremely close positioning of such thru-holes and signal lines and/or pads may result in discontinuities occurring therein, which will adversely affect the successful operation of the product, especially at high frequencies (which are also demanded in many products today). These structures may result in signal degradation, particularly, as stated, when the signal lines and/or thru-holes are positioned in close proximity to one another. The successful elimination of such discontinuities is thus highly desired for many of today's circuitized substrates, especially those intended to pass high speed signals using high density patterns of thru-holes and/or signal lines. As defined, the method taught herein is able to form such precise resistor structures in such as way as not to adversely affect the resulting operation of closely positioned conductive thru-holes, other signal lines, etc.
It is known that in some resistor trimming operations, simultaneous electrical probing and laser trimming operations are used. Probing individual resistors on a work piece is time consuming and requires utilization of expensive capital equipment (a laser with an incorporated electrical test system). This approach also becomes impractical from a cost standpoint when the number of individual resistors is large. These systems typically further require a probe card to “cover” a specified area on the substrate (within a set distance from one resistor), but this in turn limits the number of resistors within said area to a relatively few (e.g., fifty or less). With circuitized substrates such as printed circuit boards and chip carriers requiring more and more discrete structures such as resistors, capacitors and the like as part thereof, the simultaneous probe and trim approach is now considered too costly.
As will be further understood from the following, the present invention defines a new method of providing such precise resistor values for film resistors used as part of electrical circuits on both internal and external surfaces of substrate products. Significantly, the invention is able to do so in a manner which overcomes many of the disadvantages associated with processes such as described above as well as within selected ones of the following listed documents. The citation of these documents is not an admission that any are prior art to the present invention, nor that the documents are the result of an exhaustive search of the art.
In U.S. Pat. No. 3,284,878, entitled, “Method of Forming Thin Film Resistors”, there is described a method of forming electrical resistors and more particularly to a method of adjusting the resistance of thin films by selectively removing portions thereof.
In U.S. Pat. No. 3,441,804, entitled, “Thin-Film Resistors”, there is described thin-film resistors that include a basic resistor inter-coupled with a network of selectively inter-coupled individual trimming resistors which add or subtract selected increments of resistance to that of the basic resistor. The smallest value trimming resistor provides a predetermined impedance Z1, while each other trimming resistor provides an impedance equal to a different power of two times Z1. A severable electrical conductor is associated with each trimming resistor to selectively effectively electrically connect or not connect the associated resistor into the network. The trimming resistors may be connected in series, with each severable conductor in parallel with a different trimming resistor; or the trimming resistors may be connected in parallel, with each severable conductor in series with a different trimming resistor.
In U.S. Pat. No. 3,573,703, entitled, “Resistor And Method of Adjusting Resistance”, there is described a resistor formed on an insulating support between a pair of electrode terminals, a portion of the resistor extending out of the direct field established between the electrodes. The resistance value is precisely adjusted by removing resistor material in the fringing field.
In U.S. Pat. No. 3,594,679, entitled, “Method of Making Low Noise Film Resistors And Article”, there is described a method of forming a low current noise, thin film resistor having a thin electro-conductive or resistive film applied to a dielectric substrate with a portion of the film thereafter being removed so as to increase the length to width ratio thereof. The method includes the step of rubbing, smoothing, or polishing the edges of the remaining film surrounding the area where said portion was removed with a rubber-like member whereby resistor current noise is significantly decreased.
In U.S. Pat. No. 3,947,801, entitled, “Laser-Trimmed Resistor”, there is described a laser-trimmed film resistor wherein the laser kerf terminates in an area outside the electrical current path across the resistor.
In U.S. Pat. No. 4,163,315, entitled, “Method for Forming Universal Film Resistors”, there is described a method for forming a film resistor for hybrid circuits trimmable from 0 ohms to infinite resistance, whereby resistive material is deposited over previously applied conductive material. One edge of the resistor material is flush with one edge of the conductor path and the resistor material extends beyond the opposite side of the conductor path. The resistor is trimmed to value by a laser or mechanically abrading a slot in its center perpendicular to the conductor by simultaneously removing a portion of both conductor and resistive material.
In U.S. Pat. No. 4,338,590, entitled, “Multi Stage Resistive Ladder Network Having Extra Stages For Trimming”, there is described a multi-stage resistive ladder network which uses extra stages to trim out resistance discrepancies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.
In U.S. Pat. No. 4,906,966, entitled, “Trimming Resistor Network”, there is described a trimming resistor network including first and second external connection terminals, a first resistor having two ends acting as first and second connection terminals, a first coupling body for connecting the first external connection terminal to the first connection terminal via series-connected resistors, a second coupling body for connecting the second external connection terminal to the second connection terminal directly or via series-connected resistors, and parallel trimming resistors having two ends respectively connected to the first and second coupling bodies. The combined resistance between the first and second external connection terminals is increased by substantially a preset amount each time one of the parallel trimming resistors is cut off.
In U.S. Pat. No. 5,295,387, entitled, “Active Resistor Trimming of Accelerometer Circuit”, there is described a micro-machined accelerometer unit and a hybrid accelerometer circuit for processing a signal from the unit mounted in the same package with the substrate of the hybrid circuit in a plane normal to the sensitivity axis of the accelerometer. For calibration, thick film resistors on the substrate are laser trimmed at two different temperatures in two stations. The package is mounted on a shaker table with the substrate normal to the direction of vibration and a trimming laser beam normal to the substrate is directed onto the substrate to trim the resistors while the package is being vibrated. The AC (alternating current) signal produced by the circuit is monitored by test equipment and compared to a reference value to determine any signal error and to control the laser beam. The laser beam has a finite range where the depth of focus is suitable for resistor trimming and the amplitude of vibration is much smaller than that range to permit trimming during the mechanical excitation. Alternatively, the amplitude of vibration is larger than the depth of focus and the operation of the laser is synchronized with the motion of the substrate to turn on the laser only when the resistor being trimmed is within the range of the depth of focus.
In U.S. Pat. No. 5,757,264, entitled, “Electrically Adjustable Resistor Structure”, there is described a resistor structure which resistance value is electrically adjusted after fabrication by a tester during the test operation so that its equivalent resistance closely approximates a desired nominal value. The resistor structure includes a main resistor and a number of trimming resistors connected in parallel. Each trimming resistor can be connected in parallel to the main resistor independently of one another via a switch, typically a pass-gate NFET device, and serially connected therewith. The switch is enabled via a control line coupled to a binary storage cell. It includes a programmable fuse that can be electrically blown by the tester. Because the resistance value of the main resistor and trimming resistors changes as a result of fabrication process variations, the trimming resistors are designed so that no matter what the equivalent resistance value of the main resistor is, there exist an appropriate combination of trimming resistors to achieve the desired nominal value. This resistor structure is well suited for IC terminator chips.
In U.S. Pat. No. 5,808,272, entitled, “Laser System For Functional Trimming Of Films and Devices”, there is described a laser system and processing method which exploits a wavelength range in which devices, including any semiconductor material-based devices affected by conventional laser wavelengths and devices having light-sensitive or photo-electronic portions integrated into their circuits, can be effectively functionally trimmed without inducing performance drift or malfunctions in the processed devices. True measurement values of operational parameters of the devices can, therefore, be obtained without delay for device recovery, i.e., can be obtained substantially instantaneously with laser impingement. Accordingly, the present invention allows faster functional laser processing, eases geometric restrictions on circuit design, and facilitates production of denser and smaller devices.
In U.S. Pat. No. 5,994,997, entitled, “Thick Film Resistor Having Concentric Terminals And Method Therefor”, there is described a thick-film resistor and a process for forming the resistor to have accurate dimensions, thereby yielding a precise resistance value. The resistor generally includes an electrically resistive layer and a pair of terminals, a first of which is surrounded by the second terminal, so as to form a region there-between that surrounds the first terminal and separates the first and second terminals. The terminals are preferably concentric, with the second terminal and the region there-between being annular-shaped. The resistive layer electrically connects the first and second terminals to complete the resistor. Each of the terminals has a surface that is substantially parallel to an upper and/or lower surface of the resistive layer and contacts the resistive layer. The surfaces of the terminals may be embedded in the resistive layer by printing the resistive material over the terminals, or may contact the upper or lower surface of the resistive layer by locating the terminals above or below the resistive layer. In each of these embodiments, the terminals are not limited to having edge-to-edge contact with the resistive layer, such that the interfacial resistance there-between is minimized.
In U.S. Pat. No. 6,021,050, entitled “Printed Circuit Boards With Integrated Passive Components And Method Of Making Same,” there is described a multi-layered printed circuit board having a plurality of buried passive elements and a method for producing the circuit board wherein the passive elements can include resistors, capacitors and inductors. The method includes the steps of manufacturing individual layers of the multi-layer printed circuit board with electrical circuits thereon and subsequently screening polymer inks having resistive, dielectric or magnetic values to form the resistors, capacitors and inductors. Each layer of the circuit board is cured to dry the polymer ink and thereafter the individual layers are bonded together to form the multi-layer board.
In U.S. Pat. No. 6,047,463, entitled, “Embedded Trimmable Resistors”, there is defined a resistor which may be embedded into a substrate. A portion of the resistor may be exposed, by segmenting the substrate, for instance, so that the resistor may be trimmed to a desired resistance level. Alternatively, a portion of a resistor may be embedded into a substrate, with another portion of the resistor being disposed on the outer surface of the substrate. The portion of the resistor on the outer surface may be trimmed to adjust the resistance of the resistor to a desired level.
In U.S. Pat. No. 6,396,387, entitled “Resistors For Electronic Packaging” and issued May 28, 2002, there are described thin layer resistors which are formed on an insulating substrate, which resistors may be embedded within a printed circuit board. Preferred resistive materials are homogeneous mixtures of metals, such as platinum, and dielectric materials, such as silica or alumina. Even minor amounts of dielectric material admixed with a metal significantly increase the resistance of the metal. Preferably, the resistive material is deposited on the insulating substrate by combustion chemical vapor deposition (CCVD). In the case of zero valence metals and dielectric material, the homogeneous mixture is achieved by co-deposition of the metal and dielectric material by CCVD. To form discrete patches of the resistive material, substantially any metal-based resistor material, including those based on the noble metals, can be etched away. Thus, a layer of resistive material may be covered with a patterned resist, e.g., an exposed and developed photo-resist, and exposed portions of the underlying layer of resistive material etched away. This patent also describes the formation of thin layer resistors including the insulating substrate, discrete patches of a layer of resistive material, and conductive material in electrical contact with spaced-apart locations on the patches of resistive material layer, such conductive material providing for electrical connection of the resistive material patches with electronic circuitry. Such structures of insulating material, resistive material, and conductive material may be formed by selective etching procedures.
In U.S. Pat. No. 6,452,478, entitled, “Voltage Trimmable Resistor”, there is described an adjustable resistor between a first terminal and a second terminal. Generally, a plurality of resistors is provided comprising a set of trimmable resistors, where the trimmable resistors are electrically connected together in series, and a set of static resistors, where each static resistor is connected in parallel with a trimmable resistor of the set of trimmable resistors. A trim terminal and a plurality of diodes where each diode is electrically connected between a trimmable resistor and a trim terminal are also provided.
In U.S. Pat. No. 6,500,350, entitled “Formation of Thin Film Resistors” and issued Dec. 31, 2002, there is described a method for forming a patterned layer of resistive material in electrical contact with a layer of electrically conducting material. A three-layer structure is formed which comprises a metal conductive layer, an intermediate layer formed of material which is degradable by a chemical etchant, and a layer of resistive material of sufficient porosity such that the chemical etchant for the intermediate layer may seep through the resistive material and chemically degrade the intermediate layer so that the resistive material may be ablated from the conductive layer wherever the intermediate layer is chemically degraded. A patterned photo-resist layer is formed on the resistive material layer. The resistive material layer is exposed to the chemical etchant for the intermediate layer so that the etchant seeps through the porous resistive material layer and degrades the intermediate layer. Then, portions of the resistive material layer are ablated away wherever the intermediate layer has been degraded.
In U.S. Pat. No. 6,534,743, entitled, “Resistor Trimming With Small Uniform Spot From Solid-State UV Laser”, there is described a uniform laser spot, such as from an imaged shaped Gaussian output (118) or a clipped Gaussian spot, that is less than twenty microns in diameter which can be employed for both thin and thick film resistor trimming to substantially reduce micro-cracking. These spots can be generated in an ablative, non-thermal, UV laser wavelength to reduce the HAZ and/or shift in TCR.
In U.S. Pat. No. 6,539,613, entitled, “Method of Forming Trimmable Resistors”, there is described a method of forming trimmable resistors, resistor may be embedded into a substrate. A portion of the resistor may be exposed, by segmenting the substrate, so that the resistor may be trimmed to a desired resistance level. Alternatively, a portion of a resistor may be embedded into a substrate, with another portion of the resistor being disposed on the outer surface of the substrate. The portion of the resistor on the outer surface may be trimmed to adjust the resistance of the resistor to a desired level.
In U.S. Pat. No. 6,740,701, entitled “Resistive Film”, there is described a resistive film for use in a potentiometer. The film is in contact with a movable wiper. The film includes a cured polymer resin and a cured thermosetting resin. Conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resins to be electrically resistive. Carbon nano-particles are also dispersed in the film. The nano-particles increase the wear resistance of the resistive film and reduce electrical noise as the wiper moves across the film. In the preparation of an exemplary composition, a polymer solution is made by mixing 10-20 wt. percent of a polymer and 0-10 wt. percent thermosetting resin in 60-80 wt. percent N-methyl pyrrolidone, based upon the total composition. The polymer is mixed with both the conductive and nano-particles to form a paste with a fine particle size. At this point, surfactants and rheological additives may be added if desired to modify the properties of the resistive composition. The particle size range and viscosity of the paste is monitored to get a resistive paste suitable for application in position sensors. The milling time and milling quantity on the ball mill determines the final particle distribution, size and resulting rheology.
In U.S. Pat. No. 6,746,508, entitled, “Nanosized Intermetallic Powders,” there is described the use of nanoparticles of intermetallic alloys such as FeAl, Fe3Al, NiAl, TiAl and FeCoV which exhibit a wide variety of interesting structural, magnetic, catalytic, resistive and electronic, and bar coding applications. The nanosized powders can be used to make structural parts having enhanced mechanical properties, magnetic parts having enhanced magnetic saturation, catalyst materials having enhanced catalytic activity, thick film circuit elements having enhanced resolution, and screen printed images such as magnetic bar codes having enhanced magnetic properties. In contrast to bulk FeAl materials which are nonmagnetic at room temperature, the FeAl nanoparticles exhibit magnetic properties at room temperature.
In U.S. Pat. No. 6,940,038, entitled “Laser Trimming of Resistors”, there is described a method for laser trimming resistors printed on a substrate layer. In one embodiment, a resistance value is measured for each annular resistor and sorts the annular resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor to the respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.
In U.S. Pat. No. 7,235,745, entitled, “Resistor Material With Metal Component For Use In Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling Utilizing Said Circuitized Substrate”, there is described a material for use as part of an internal resistor within a circuitized substrate which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. A circuitized substrate adapted for using such a material and resistor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided. U.S. Pat. No. 7,235,745 is assigned to the same Assignee as the present invention.
In U.S. Patent Application Publication 2003/0146418 A1, entitled “Resistive Film,” there is described a resistive film for use in a potentiometer. The film is in contact with a movable wiper. The film includes a cured polymer resin and a cured thermosetting resin. Conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resins to be electrically resistive. Carbon nano-particles are also dispersed in the film. The nano-particles increase the wear resistance of the resistive film and reduce electrical noise as the wiper moves across the film.
In U.S. Patent Application Publication 2005/0000728 A1, entitled “Wiring Board Provided With A Resistor And Process For Manufacturing The Same,” there is described a wiring board provided with a resistor, The board comprises an insulating substrate having a surface, wiring patterns formed on the surface, the wiring patterns including first and second electrodes spaced from each other by a certain distance, a first resistor (horizontal type resistor) formed on the surface, the first resistor having respective ends connected with the first and second electrodes, respectively, the wiring patterns further including a third electrode, occupying a first plane area on the surface, a second resistor (vertical type resistor) formed on the third electrode, a fourth electrode formed on the second resistor, and the second resistor, the fourth electrode being located in a second plane area within the first plane area.
In U.S. Patent Application Publication 2005/0051360 A1, entitled “Polymer Thick-Film Resistive Paste, A Polymer Thick-Film Resistor And A Method And An Apparatus For The Manufacture Thereof,” there are described formulations, apparatus and a method of applying high thixotropic index polymer thick-film resistive pastes for making polymer thick-film resistors with improved tolerances by providing a squeegee with a blade tilted at an angle of 10 to 85 to the surface of the printed circuit board. The tilted blade causes a fluid rotational motion within the bead of the polymer thick-film resistive paste as the squeegee blade moves relative to the printed circuit board. This rotational motion increases the shear strain rate experienced by the paste within the bead and results in a more effective filling of the resistor-shaped cavity without including air bubbles, experiencing elastic recovery of the paste and, without surface fractures of the paste.
In U.S. Patent Application Publication 2006/0205121 A1, entitled, “Method and System For High-Speed, Precise Micromachining An Array Of Devices”, there is described a method and system for high-speed, precise micromachining an array of devices wherein improved process throughput and accuracy, such as resistor trimming accuracy, are provided. The number of resistance measurements is limited by using non-measurement cuts, using non-sequential collinear cutting, using spot fan-out parallel cutting, and using a retrograde scanning technique for faster collinear cuts. Non-sequential cutting is also used to manage thermal effects and calibrated cuts are used for improved accuracy. Test voltage is controlled to avoid resistor damage.
The teachings of the above patents, publications and cited co-pending applications are incorporated herein by reference.
It is believed that a method as taught herein will represent a significant advancement in the art. As understood from the following description, this method obviates many of the disadvantages associated with methods known in the art such as many of those discussed in the foregoing documents.